Tunable contact resistance in double-gate organic field-effect transistorsYONG XU; DARMAWAN, Peter; CHUAN LIU et al.Organic electronics (Print). 2012, Vol 13, Num 9, pp 1583-1588, issn 1566-1199, 6 p.Article

Optimum crystallographic alignment for Si n-Channel ballistic DGFETsLAUX, S. E.IEEE electron device letters. 2005, Vol 26, Num 9, pp 679-681, issn 0741-3106, 3 p.Article

Justifying threshold voltage definition for undoped body transistors through crossover point conceptRATUL KUMAR BARUAH; MAHAPATRA, Santanu.Physica. B, Condensed matter. 2009, Vol 404, Num 8-11, pp 1029-1032, issn 0921-4526, 4 p.Article

Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel ThicknessLIN, Homg-Chih; CHEN, Wei-Chen; HUANG, Tiao-Yuan et al.IEEE electron device letters. 2009, Vol 30, Num 6, pp 644-646, issn 0741-3106, 3 p.Article

A simple modelling of device speed in double-gate SOI MOSFETsRAJENDRAN, K; SAMUDRA, G.Microelectronics journal. 2000, Vol 31, Num 4, pp 255-259, issn 0959-8324Article

Form factor increase and its physical origins in electron-modulated acoustic phonon interaction in a free-standing semiconductor plateUNO, Shigeyasu; HATTORI, Junichi; NAKAZATO, Kazuo et al.Mathematical and computer modelling. 2010, Vol 51, Num 7-8, pp 863-872, issn 0895-7177, 10 p.Article

Full quantum treatment of surface roughness effects in Silicon nanowire and double gate FETsPALA, Marco G; BURAN, Claudio; POLI, Stefano et al.Journal of computational electronics (Print). 2009, Vol 8, Num 3-4, pp 374-381, issn 1569-8025, 8 p.Article

Threshold voltages of SOI MuGFETsDE ANDRADE, Maria Gloria Cano; MARTINO, Joao Antonio.Solid-state electronics. 2008, Vol 52, Num 12, pp 1877-1883, issn 0038-1101, 7 p.Conference Paper

Electric potential and threshold voltage models for double-gate Schottky-barrier source/drain MOSFETsPEICHENG LI; GUANGXI HU; RAN LIU et al.Microelectronics journal. 2011, Vol 42, Num 10, pp 1164-1168, issn 0959-8324, 5 p.Article

High-performance top and bottom double-gate low-temperature poly-silicon thin film transistors fabricated by excimer laser crystallizationTSAI, Chun-Chien; LEE, Yao-Jen; WANG, Jyh-Liang et al.Solid-state electronics. 2008, Vol 52, Num 3, pp 365-371, issn 0038-1101, 7 p.Conference Paper

An analytic model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETsZHIHAO DING; GUANGXI HU; JINGLUN GU et al.Microelectronics journal. 2011, Vol 42, Num 3, pp 515-519, issn 0959-8324, 5 p.Article

Three-level stencil alignment fabrication of a high-k gate stack organic thin film transistorCVETKOVIC, Nenad V; SIDLER, Katrin; SAVU, Veronica et al.Microelectronic engineering. 2011, Vol 88, Num 8, pp 2496-2499, issn 0167-9317, 4 p.Conference Paper

Double-gate pentacene thin-film transistor with improved control in sub-threshold regionTSAMADOS, Dimitrios; CVETKOVIC, Nenad V; SIDLER, Katrin et al.Solid-state electronics. 2010, Vol 54, Num 9, pp 1003-1009, issn 0038-1101, 7 p.Conference Paper

Optimal Dual-V_T Design in Sub-100-nm PD/SOI and Double-Gate TechnologiesBANSAL, Aditya; KIM, Jae-Joon; KIM, Keunwoo et al.I.E.E.E. transactions on electron devices. 2008, Vol 55, Num 5, pp 1161-1169, issn 0018-9383, 9 p.Article

Capacitance modeling of short-channel double-gate MOSFETsBØRLI, Hakon; KOLBERG, Sigbjørn; FJELDLY, Tor A et al.Solid-state electronics. 2008, Vol 52, Num 10, pp 1486-1490, issn 0038-1101, 5 p.Conference Paper

Multiple gate devices : advantages and challengesPOIROUX, T; VINET, M; FAYNOT, O et al.Microelectronic engineering. 2005, Vol 80, pp 378-385, issn 0167-9317, 8 p.Conference Paper

A stacked CMOS technology on SOI substrateSHENGDONG ZHANG; RUQI HAN; XINNAN LIN et al.IEEE electron device letters. 2004, Vol 25, Num 9, pp 661-663, issn 0741-3106, 3 p.Article

TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFETRUPENDRA KUMAR SHARMA; MRIDULA GUPTA; GUPTA, R. S et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 9, pp 2936-2943, issn 0018-9383, 8 p.Article

Quantum Analytical Model for Inversion Charge and Threshold Voltage of Short-Channel Dual-Material Double-Gate SON MOSFETNASKAR, Sourav; SUBIR KUMAR SARKAR.I.E.E.E. transactions on electron devices. 2013, Vol 60, Num 9, pp 2734-2740, issn 0018-9383, 7 p.Article

Device Design Engineering for Optimum Analog/RF Performance of Nanoscale DG MOSFETsSHARMA, Rupendra Kumar; BUCHER, Matthias.IEEE transactions on nanotechnology. 2012, Vol 11, Num 5, pp 992-998, issn 1536-125X, 7 p.Article

Analytical unified threshold voltage model of short-channel FinFETs and implementationFASARAKIS, N; TSORMPATZOGLOU, A; TASSIS, D. H et al.Solid-state electronics. 2011, Vol 64, Num 1, pp 34-41, issn 0038-1101, 8 p.Article

Comparison and improvement of two core compact models for double-gate MOSFETsXINGYE ZHOU; ZHIZE ZHOU; JIAN ZHANG et al.Solid-state electronics. 2010, Vol 54, Num 11, pp 1444-1446, issn 0038-1101, 3 p.Article

Explicit analytical charge and capacitance models of undoped double-gate MOSFETsMOLDOVAN, Oana; JIMENEZ, David; ROIG GUITART, Jaume et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 7, pp 1718-1724, issn 0018-9383, 7 p.Article

A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFETMUKHOPADHYAY, Saibal; MAHMOODI, Hamid; ROY, Kaushik et al.IEEE transactions on very large scale integration (VLSI) systems. 2006, Vol 14, Num 2, pp 183-192, issn 1063-8210, 10 p.Article

Unification of asymmetric DG, symmetric DG and bulk undoped-body MOSFET drain currentORTIZ-CONDE, Adelmo; GARCIA SANCHEZ, Francisco J.Solid-state electronics. 2006, Vol 50, Num 11-12, pp 1796-1800, issn 0038-1101, 5 p.Article